SystemVerilog

Raised as a usability problem by 5 people on Hacker News over 7 years (2020–2026), in 5 threads.

People raised many different problems with SystemVerilog, but no single problem has yet been raised by 3 people in 3 different months and threads.

Unreviewed issues were grouped by machine: Claude Haiku labelled each comment as a usability complaint, named what it's about and summed up the problem in a line, and a small model grouped similar problems. Nobody has checked them by hand. Expect mistakes.

The newest 5 complaints

Full of footguns, gotchas, and undocumented tool-dependent behavior hard to learn2026-08-11
Mixed assignment types and metaprogramming layer make it hard to describe hardware correctly2025-08-06
Hard to write parameterized functions on type or width that synthesize2021-11-26
Verification tooling is too complex and bloated for hardware testing2021-03-11
Confusing, redundant language constructs whose purpose and behavior are unclear2020-10-28